#ifndef __BOARD_H__
#define __BOARD_H__

#include "device/sbarmsoc_sb3500.h"

#define readb(addr) (*(volatile unsigned char *)(addr))
#define readw(addr) (*(volatile unsigned short *)(addr))
#define readl(addr) (*(volatile unsigned int *)(addr))



#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
#define writel(b,addr) (void)((*(volatile unsigned long *) (addr)) = (b))

#define OSC_XTAL_FREQ         30720000
#define OSC_PMCLK             1544000

#define SBARMSOC_MMIO_BASE    0x80000000

/*
 * AHB peripherals
 */
#define SBARMSOC_MMIO_HAB     (SBARMSOC_MMIO_BASE|0x08000000)
#define SBARMSOC_MMIO_LCDC    (SBARMSOC_MMIO_BASE|0x08001000)
#define SBARMSOC_MMIO_SDIO    (SBARMSOC_MMIO_BASE|0x08002000)
#define SBARMSOC_MMIO_DMAC    (SBARMSOC_MMIO_BASE|0x08003000)
#define SBARMSOC_MMIO_VIC     (SBARMSOC_MMIO_BASE|0x08005000)
#define SBARMSOC_MMIO_USB     (SBARMSOC_MMIO_BASE|0x08006000)
#define SBARMSOC_MMIO_DC      (SBARMSOC_MMIO_BASE|0x08007000)
#define SBARMSOC_MMIO_CAMERA  (SBARMSOC_MMIO_BASE|0x08008000)
#define SBARMSOC_MMIO_API     (SBARMSOC_MMIO_BASE|0x0800A000)


/* UART */
#define SERIAL_BASE           SBARMSOC_MMIO_UART1    /* UART 1 base address */
#define UART_BASE             SBARMSOC_MMIO_UART2    /* UART 2 base address */


/* DPMU */
#define DPMU_BASE             SBARMSOC_MMIO_DPMU
#define DPMU_REG(offset)      (DPMU_BASE + offset)
#define DPMU_SEQ_START        0x02c  /* sleep and execute cmd */
#define DPMU_SBX1_CTRL        0x030  /* sbx 1 clock gate/reset/dmu */
#define DPMU_SBX2_CTRL        0x034  /* sbx 2 clock gate/reset/dmu */
#define DPMU_SBX3_CTRL        0x038  /* sbx 3 clock gate/reset/dmu */
#define DPMU_ARM_CTRL         0x03c  /* ARM clock gate/reset/pg */
#define DPMU_SH_CLK           0x040  /* HSN SBX3 SBX2 SBX1 */
#define DPMU_SOC_CTRL         0x044  /* HSN, abp, ahb, axi */
#define DPMU_PLL_CTRL         0x048  /* pll setting */
#define DPMU_AMBA_CLK         0x04c  /* smc, dmc, apb, ahb, axi clks */
#define DPMU_AMBA_CKG         0x050  /* smc, dmc, apb, ahb, axi clks */
#define DPMU_PAD_SHARE        0x054  /* changes some PADS */
#define DPMU_PAD_CNTL         0x058  /* DDR pad control 0xE worked */
#define DPMU_RTC_DATA         0x060  /* read real time counter */
#define DPMU_RTC_MATCH        0x064  /* interrupt when counter match */
#define DPMU_RTC_CHG          0x068  /* update counter */
#define DPMU_RTC_CTRL         0x06c  /* interrupt control */
#define DPMU_WDOG_CTRL        0x07c
#define DPMU_WDOG_DATA_L      0x080
#define DPMU_WDOG_DATA_H      0x084   /*UPPER 16 BIT.*/
#define DPMU_WDOG_INIT_L      0x088
#define DPMU_WDOG_INIT_H      0x08c
#define DPMU_WDOG_REFRESH     0x090
#define DPMU_ETMR1_INIT       0x110  /* timer 1 initial value */
#define DPMU_ETMR1_CTRL       0x118  /* timer 1 control register */
#define DPMU_ETMR1_COUNT      0x11c  /* timer 1 read count */
#define DPMU_ETMR1_MTCH1      0x120  /* timer 1 Match 1 PmPsdEN */
#define DPMU_ETMR1_MTCH2      0x124  /* timer 1 Match 2 PmPsdDMA 1 */
#define DPMU_ETMR1_MTCH3      0x128  /* timer 1 Match 3 PmPsdDMA 0 */
#define DPMU_ETMR2_INIT       0x130  /* timer 2 initial value */
#define DPMU_ETMR2_CTRL       0x138  /* timer 2 control register */
#define DPMU_ETMR2_COUNT      0x13c  /* timer 2 read count */
#define DPMU_ETMR2_MTCH1      0x140  /* timer 2 Match 1 PmPsdEN */
#define DPMU_ETMR2_MTCH2      0x144  /* timer 2 Match 2 PmPsdDMA 1 */
#define DPMU_ETMR2_MTCH3      0x148  /* timer 2 Match 3 PmPsdDMA 0 */
#define DPMU_ETMR3_INIT       0x150  /* timer 3 initial value */
#define DPMU_ETMR3_CTRL       0x158  /* timer 3 control register */
#define DPMU_ETMR3_COUNT      0x15c  /* timer 3 read count */
#define DPMU_ETMR3_MTCH1      0x160  /* timer 3 Match 1 PmPsdEN */
#define DPMU_ETMR3_MTCH2      0x164  /* timer 3 Match 2 PmPsdDMA 1 */
#define DPMU_ETMR3_MTCH3      0x168  /* timer 3 Match 3 PmPsdDMA 0 */
#define DPMU_ETMR4_INIT       0x170  /* timer 4 initial value */
#define DPMU_ETMR4_CTRL       0x178  /* timer 4 control register */
#define DPMU_ETMR4_COUNT      0x17c  /* timer 4 read count */
#define DPMU_ETMR4_MTCH1      0x180  /* timer 4 Match 1 PmPsdEN */
#define DPMU_ETMR4_MTCH2      0x184  /* timer 4 Match 2 PmPsdDMA 1 */
#define DPMU_ETMR4_MTCH3      0x188  /* timer 4 Match 3 PmPsdDMA 0 */
#define DPMU_SEQ_MEMORY       0x200  /* sequencer memory */


/* USB */
#define USB_BASE              SBARMSOC_MMIO_USB


/* DEVICE CONTROL */
#define DC_BASE               SBARMSOC_MMIO_DC
#define DC_REG(offset)        (DC_BASE + offset)
#define DC_AMBA_RST           0x000
#define DC_PAD_CTRL           0x004
#define DC_DSP_INT            0x008
#define DC_DRF_IRQ            0x00C
#define DC_CLK_EN             0x010
#define DC_DRF_EN             0x014
#define DC_SDIO_CFG           0x018
#define DC_PSD_SHARE          0x01c
#define DC_ETM_CTRL           0x034
#define DC_NODE_TIMER_INTR    0x038
#define DC_ARB_STARVE         0x03c


/* DDR */
#define MEM_BASE              0x40000000
#define MEM_SIZE              0x08000000


/* TIMER */
#define TICK_BASE             SBARMSOC_MMIO_COUNT1
#define TICK_REG(offset)      (TICK_BASE + offset)

#define TIMER_BASE            SBARMSOC_MMIO_COUNT2
#define TIMER_REG(offset)     (TIMER_BASE + offset)

#define CNT_DATA              0x000
#define CNT_MATCH             0x004
#define CNT_CTRL              0x008
#define CNT_RAW_INTR          0x00c
#define CNT_MASK_INTR         0x010
#define CNT_CLR_INTR          0x014


/* DMC */
#define DMC_MEMC_STATUS       0x000
#define DMC_MEMC_CMD          0x004
#define DMC_DIRECT_CMD        0x008
#define DMC_MEMORY_CFG        0x00c
#define DMC_REFRESH_PRD       0x010
#define DMC_CAS_LATENCY       0x014
#define DMC_T_DQSS            0x018
#define DMC_T_MRD             0x01c
#define DMC_T_RAS             0x020
#define DMC_T_RC              0x024
#define DMC_T_RCD             0x028
#define DMC_T_RFC             0x02c
#define DMC_T_RP              0x030
#define DMC_T_RRD             0x034
#define DMC_T_WR              0x038
#define DMC_T_WTR             0x03c
#define DMC_T_XP              0x040
#define DMC_T_XSR             0x044
#define DMC_T_ESR             0x048
#define DMC_MEMORY_CFG2       0x04c
#define DMC_MEMORY_CFG3       0x050
#define DMC_CHIP_0_CFG        0x200
#define DMC_CHIP_1_CFG        0x204
#define DMC_CHIP_2_CFG        0x208
#define DMC_CHIP_3_CFG        0x20c
#define DMC_USER_STATUS       0x300


/* SMC */
#define SMC_MEMC_STATUS       0x000
#define SMC_MEMIF_CFG         0x004
#define SMC_MEMC_CFG_SET      0x008
#define SMC_MEMC_CFG_CLR      0x00c
#define SMC_DIRECT_CMD        0x010
#define SMC_SET_CYCLES        0x014
#define SMC_SET_OPMODE        0x018
#define SMC_REFRESH_PERIOD_0  0x020
#define SMC_REFRESH_PERIOD_1  0x024

#define SMC_SRAM_CYCLES_I0C0  0x100
#define SMC_SRAM_CYCLES_I0C1  0x120
#define SMC_SRAM_CYCLES_I0C2  0x140
#define SMC_SRAM_CYCLES_I0C3  0x160
#define SMC_SRAM_CYCLES_I1C0  0x180
#define SMC_SRAM_CYCLES_I1C1  0x1a0
#define SMC_SRAM_CYCLES_I1C2  0x1c0
#define SMC_SRAM_CYCLES_I1C3  0x1e0

#define SMC_NAND_CYCLES_I0C0  0x100
#define SMC_NAND_CYCLES_I0C1  0x120
#define SMC_NAND_CYCLES_I0C2  0x140
#define SMC_NAND_CYCLES_I0C3  0x160
#define SMC_NAND_CYCLES_I1C0  0x180
#define SMC_NAND_CYCLES_I1C1  0x1a0
#define SMC_NAND_CYCLES_I1C2  0x1c0
#define SMC_NAND_CYCLES_I1C3  0x1e0

#define SMC_OPMODE_I0C0       0x104
#define SMC_OPMODE_I0C1       0x124
#define SMC_OPMODE_I0C2       0x144
#define SMC_OPMODE_I0C3       0x164
#define SMC_OPMODE_I1C0       0x184
#define SMC_OPMODE_I1C1       0x1a4
#define SMC_OPMODE_I1C2       0x1c4
#define SMC_OPMODE_I1C3       0x1e4

#define SMC_USER_STATUS       0x200
#define SMC_USER_CONFIG       0x204

#define SMC_ECC_STATUS_I0     0x300
#define SMC_ECC_MEMCFG_I0     0x304
#define SMC_ECC_MEMCMD1_I0    0x308
#define SMC_ECC_MEMCMD2_I0    0x30c
#define SMC_ECC_ADDR0_I0      0x310
#define SMC_ECC_ADDR1_I0      0x314
#define SMC_ECC_VALUE0_I0     0x318
#define SMC_ECC_VALUE1_I0     0x31c
#define SMC_ECC_VALUE2_I0     0x320
#define SMC_ECC_VALUE3_I0     0x324
#define SMC_ECC_VALUE4_I0     0x328

#define SMC_ECC_STATUS_I1     0x400
#define SMC_ECC_MEMCFG_I1     0x404
#define SMC_ECC_MEMCMD1_I1    0x408
#define SMC_ECC_MEMCMD2_I1    0x40c
#define SMC_ECC_ADDR0_I1      0x410
#define SMC_ECC_ADDR1_I1      0x414
#define SMC_ECC_VALUE0_I1     0x418
#define SMC_ECC_VALUE1_I1     0x41c
#define SMC_ECC_VALUE2_I1     0x420
#define SMC_ECC_VALUE3_I1     0x424
#define SMC_ECC_VALUE4_I1     0x428

#define SMC_INTEGRATION_TEST  0xe00

#define SMC_PERIPHID0         0xfe0
#define SMC_PERIPHID1         0xfe4
#define SMC_PERIPHID2         0xfe8
#define SMC_PERIPHID3         0xfec

#define SMC_PCELLID0          0xff0
#define SMC_PCELLID1          0xff4
#define SMC_PCELLID2          0xff8
#define SMC_PCELLID3          0xffc


/* GPIO */
#define GPIO_BASE             SBARMSOC_MMIO_GPIO1
#define GPIO_OFFSET           0x1000
#define GPIO_REG(port, reg)   (SOC_GPIO_BASE + port *SOC_GPIO_OFFSET + reg)

#define AGPIO_DATA            0x000
#define AGPIO_DIR             0x400
#define AGPIO_IS              0x404
#define AGPIO_IBE             0x408
#define AGPIO_IEV             0x40c
#define AGPIO_IE              0x410
#define AGPIO_RIS             0x414
#define AGPIO_MIS             0x418
#define AGPIO_IC              0x41c
#define AGPIO_AFSEL           0x420


/* VIC */
#define VIC_BASE              SBARMSOC_MMIO_VIC
#define VIC_REG(offset)       (VIC_BASE + offset)
#define VIC_IRQ_STATUS        0x000
#define VIC_FIQ_STATUS        0x004
#define VIC_RAW_INTR          0x008
#define VIC_INT_SELECT        0x00c /* 1 = FIQ, 0 = IRQ */
#define VIC_INT_ENABLE        0x010 /* 1 = enable, 0 = disable */
#define VIC_INT_ENABLE_CLEAR  0x014
#define VIC_INT_SOFT          0x018
#define VIC_INT_SOFT_CLEAR    0x01c
#define VIC_PROTECT           0x020
#define VIC_PL190_VECT_ADDR   0x030 /* PL190 only */
#define VIC_PL190_DEF_VECT_ADDR 0x34 /* PL190 only */


#define VIC_VECT_ADDR0        0x100 /* 0 to 15 (0..31 PL192) */
#define VIC_VECT_CNTL0        0x200 /* 0 to 15 (0..31 PL192) */
#define VIC_ITCR              0x300 /* VIC test control register */

#define VIC_VECT_CNTL_ENABLE  (1 << 5)

#endif

